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1 ? fn9175.2 isl6424 dual output lnb supply and control voltage regulator with i 2 c interface for advanced satellite set-top box designs the isl6424 is a highly integrated voltage regulator and interface ic, specifically designed for supplying power and control signals from advanced satellite set-top box (stb) modules to the low noise blocks (lnbs) of two antenna ports. the device is comprised of two independent current- mode boost pwms and two low-noise linear regulators along with the circuitry required for 22khz tone generation, modulation and i 2 c device interface. the device makes the total lnb supply design simple, efficient and compact with low external component count. two independent current-mode boost converters provide the linear regulators with input volt ages that are set to the final output voltages, plus typically 1.2v to insure minimum power dissipation across each linear regulator. this maintains constant voltage drops across each linear pass element while permitting adequate voltage range for tone injection. the final regulated output voltages are available at two output terminals to support simultaneous operation of two antenna ports for dual tuners. the outputs for each pwm are set to 13v or 18v by independent voltage select commands (vsel1, vsel2) through the i 2 c bus. additionally, to compensate for the voltage drop in the coaxial cable, the selected voltage may be increas ed by 1v with the line length compensation (llc) feature. all the functions on this ic are controlled via the i 2 c bus by writing 8 bits on system register (sr, 8 bits). the same register can be read back, and two bits will report the diagnostic status. separate enable commands sent on the i 2 c bus provide independent standby mode control for each pwm and linear combination, disabling the output into shutdown mode. each output channel is capable of providing 750ma of continuous current. the overcurrent limit can be digitally programmed. the sel18v pin allows the 13v to 18v transition with an external pin, overriding the i 2 c input. the isl6424 is offered in a 32 ld 5x5 qfn. a 28 ld epsoic package is coming soon. features ? single chip power solution - true dual operation for 2-tuner/2-dish applications - both outputs may be enabled simultaneously at maximum power - integrated dc-dc converter and i 2 c interface ? switch-mode power converter for lowest dissipation - boost pwms with > 92% efficiency - selectable 13v or 18v outputs - digital cable length compensation (1v) ?i 2 c compatible interface fo r remote device control - registered slave address 0001 00xx - full 3.3v/5v operation up to 400khz ? external pins to select 13v/18v option ? dsqin1&2 and sel18v1&2 pins 2.5v logic compatible ? built-in tone oscillator factory trimmed to 22khz - facilitates diseqc (eutelsat) encoding ? internal over-temperature protection and diagnostics ? internal overload and overtemp flags (visible on i 2 c) ? lnb short-circuit protection and diagnostics ? qfn package - compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - near chip-scale package footprint ? pb-free available (rohs compliant) applications ? lnb power supply and control for satellite set-top box references ? tech brief 389 (tb389) - ?pcb land pattern design and surface mount guidelines for qfn packages?; available on the intersil website, www.intersil.com ordering information part # temp. (c) package pkg. dwg. # isl6424eeb -20 to 85 28 ld epsoic m28.3b ISL6424EEBZ (note 1) -20 to 85 28 ld epsoic (pb-free) m28.3b isl6424er -20 to 85 32 ld 5x5 qfn l32.5x5 isl6424erz (note 1) -20 to 85 32 ld 5x5 qfn (pb-free) l32.5x5 notes: 1. intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, wh ich are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. add ?-t? suffix for tape and reel packing option. data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004-2005. all rights reserved all other trademarks mentioned are the property of their respective owners. april 13, 2005
2 fn9175.2 april 13, 2005 pinouts isl6424 (epsoic) top view isl6424 (qfn) top view vsw2 comp2 fb2 gate2 cs2 sgnd sel18v1 sel18v2 bypass gate1 cs1 fb1 comp1 vsw1 vcc cpswin cpswout tcap2 dsqin2 agnd dsqin1 tcap1 scl addr sda cpvout vo2 vo1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 isl6424eeb note: the pgnd is connected to the bottom e pad and should be soldered appropriately to the gnd plane on the pwb. pgnd2 cs2 sgnd sel18v1 sel18v2 byp pgnd1 gate1 cpswout tcap2 dsqin2 vo2 agnd vo1 dsqin1 tcap1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 910111213141516 cs1 fb1 comp1 vsw1 nc addr sda isl6424er scl cpswin cpvout vcc nc vsw2 fb2 comp2 gate2 isl6424
3 fn9175.2 april 13, 2005 block diagram notes: 3. pinouts shown are for the epsoic package. 4. the qfn package has 2 additi onal pins: sel18v1 and sel18v2. counter overcurrent protection logic scheme 1 olf1 dcl oc1 clk1 pwm logic q s gate1 pgnd1 cs1 cs amp ilim1 slope compensation 2 3 5 epad 10 11 12 13 15 16 17 18 19 20 22 24 25 26 27 28 comp1 fb1 vo1 vcc sgnd bypass + - ent1 ent2 overcurrent protection logic scheme 2 counter olf2 dcl oc2 clk2 pwm logic q s gate2 pgnd2 cs2 comp2 fb2 vsw2 vo2 cpvout cpswin cpswout 4 charge pump thermal shutdown otf olf1 sda isel1 en1 otf llc1 vsel1 vsel2 llc2 dcl ent2 en2 isel2 scl addr ent1 osc. 220khz clk1 clk2 i 2 c interface band gap ref voltage adj1 ref voltage tone inj ckt 1 22khz tone tone inj ckt 2 23 dsqin1 dsqin2 tcap2 tcap1 10 & wave shaping agnd adj2 ref voltage bgv + - + - en1/en2 soft-start int 5v on chip linear uvlo por soft-start 6 14 vsw1 1 + - bgv cs amp ilim2 slope compensation + - 21 9 vref2 vref1 sda addr scl + - olf2 epad sel18v1 8 sel18v2 7 isl6424
4 fn9175.2 april 13, 2005 typical applicati on schematic epsoic c22 0.1uf sel18v2 8 bypass 9 sel18v1 7 cs1 11 gate1 10 fb1 12 dsqin1 19 tcap1 18 addr 16 vsw1 14 sda 15 fb2 3 comp1 13 vo1 20 gate2 4 cs2 5 vo2 22 agnd 21 epad 29 vsw2 1 comp2 2 dsqin2 23 sgnd 6 tcap2 24 cpswout 25 cpswin 26 vcc 28 cpvout 27 scl 17 u1 isl6424eeb 1 2 3 4 5 6 7 8 q1 fds6612a 1 2 3 4 5 6 7 8 q2 fds6612a d1 stps2l40u d2 stps2l40u d3 stps2l40u d4 stps2l40u r1 0.1 r2 0.1 r3 100 r4 18 r5 100 r6 18 r7 68k 0 0 c1 100pf r12 100k 0 r13 100k d5 stps2l40u d6 stps2l40u c10 10uf c11 10uf c12 10uf c13 10uf c14 10uf c15 10uf 0 0 0 0 scl 0 0 sda 0 0 0 sel18v2 1 2 l1 33uh 1 2 l2 33uh 0 sel18v1 c2 100pf 0 0 0 c23 33p 0 0 0 c3 56uf vin c4 56uf dsqin1 c5 56uf vin c6 56uf cmax 0 dsqin2 vin 0 c16 1uf 0 0 1 2 l3 4.7uh 1 2 l4 4.7uh c24 33p c17 47n 0 0 c7 1.5n 0 c8 1uf 0 c18 1n 0 0 r10 1k vlnb2 r11 1k r8 68k vlnb1 c9 1.5n c19 0.22uf c20 0.22uf c21 0.1uf isl6424
5 fn9175.2 april 13, 2005 typical application schematic qfn l4 100nh d2 c15 c26 1f e r6 5.1 + e e c17 56f c28a 10f c28b 10f c18 1f l2 33h c14 33pf r4 0.10 c24 100pf r10 100 1 2 3 4 8 7 6 5 q2 fds6612a c21 4.7f c12 1f e d c10 1000pf c2 1f c9 0.047f e d c8 1f 32 2 1 30 31 29 21 22 u1 isl6424 gate2 cs2 pgnd2 comp2 fb2 vsw2 vo2 dsqin2 scl sda addr sgnd nc agnd sel18v1 s e l 1 8 v 2 gate1 cs1 pgnd comp1 fb1 vsw1 vo1 dsqin1 8 9 7 11 10 12 19 18 33 ep e tcap1 vcc nc cpvout cpswin cpswout byp tcap2 17 37 38 36 35 34 6 23 16 14 15 3 13 20 4 5 d c13 1500pf c31 0.01f e r5 68k sp2 e d4 stps2l40u c19 0.1f p5 p6 vout2 gnd e r13 100k r14 100k r16 100k r17 100k r15 100k vl in sel18v1 sel18v2 p9 p8 1 2 3 4 5 6 12 11 10 9 8 7 dip_sw5_spst sw1 d disq1 disq2 sel18v1 sel18v2 addr gnd p1 p2 vin c15 10f + c15a 56f e l3 100nh d1 c3 c25 1f e r1 5.1 + e e c5 56f c27b 10f c27a 10f c4 1f l1 33h c5 33pf r2 0.10 c24 100pf r9 100 1 2 3 4 8 7 6 5 q1 fds6612a c7 1500pf c30 0.01f e r3 68k sp1 e d3 stps2l40u c21 0.1f p3 p4 vout1 gnd e vl out + c1a 56f e c1b 10f 1500pf e p7 +5v/+3.3v stps2l40u stps2l40u scl gnd gnd sda j1 1x4 1 2 3 4 1 2 3 4 c29 0.1f d r12 10k r11 10k r8 100 r7 100 isl6424
6 fn9175.2 april 13, 2005 absolute maximum rati ngs thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v to 18.0v logic input voltage range (sda, scl, ent, dsqin 1&2, sel18v 1&2) . . . . . . -0.5v to 7v thermal resistance (typical, notes 5, 6) ja (c/w) jc (c/w) epsoic package (notes 5, 6) . . . . . . . 27 2 qfn package (notes 5, 6) . . . . . . . . . . 32 4 maximum junction temperature (note 7) . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -40c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) operating temperature range . . . . . . . . . . . . . . . . . . -20c to 85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 5. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. the device junction temperature should be kept below 150c. thermal shut-down circui try turns off the device if junction temp erature exceeds +150c typically. electrical specifications v cc = 12v, t a = -20c to +85c, unless otherwise noted. typical values are at t a = 25c. en1 = en2 = h, llc1 = llc2 = l, ent1 = ent2 = l, dcl = l, dsqin1 = dsqin2 = l, iout = 12ma, unless otherwise noted. see software description section for i 2 c access to the system. parameter symbol test conditions min typ max units operating supply voltage range 81214 v standby supply current en1 = en2 = l - 1.5 3.0 ma supply current i in en1 = en2 = llc1 = llc2 = vsel1 = vsel2 = ent1 = ent2 = h, no load -4.08.0ma undervoltage lockout start threshold 7.5 - 7.95 v stop threshold 7.0 - 7.55 v start to stop hysteresis 350 400 500 mv soft-start comp rise time (note 8) (note 9) - 512 - cycles output voltage (note 9) v o1 vsel1 = l, llc1 = l 12.74 13.0 13.26 v v o1 vsel1 = l, llc1 = h 13.72 14.0 14.28 v v o1 vsel1 = h, llc1 = l 17.64 18.0 18.36 v v o1 vsel1 = h, llc1 = h 18.62 19.0 19.38 v v o2 vsel2 = l, llc2 = l 12.74 13.0 13.26 v v o2 vsel2 = l, llc2 = h 13.72 14.0 14.28 v v o2 vsel2 = h, llc2 = l 17.64 18.0 18.36 v v o2 vsel2 = h, llc2 = h 18.62 19.0 19.38 v line regulation dv o1, dv o2 v in = 8v to 14v; v o1 , v o2 = 13v - 4.0 40.0 mv v in = 8v to 14v; v o1 , v o2 = 18v - 4.0 60.0 mv load regulation dv o1, dv o2 i o = 12ma to 350ma - 50 80 mv i o = 12ma to 750ma (note 10) - 100 200 mv dynamic output current limiting i max dcl = l, isel1/2 = l 425 - 550 ma dcl = l, isel1/2 = h (note 10) 775 850 950 ma isl6424
7 fn9175.2 april 13, 2005 dynamic overload protection off time toff dc l = l, output shorted (note 10) - 900 - ms dynamic overload protection on time ton - 20 - ms 22khz tone section tone frequency f tone ent1/2 = h 20.0 22.0 24.0 khz tone amplitude v tone ent1/2 = h 500 680 800 mv tone duty cycle dc tone ent1/2 = h (note 10) 40 50 60 % tone rise or fall time t r , t f ent1/2 = h 5 8 14 s linear regulator drop-out voltage iout = 750ma (note 10) - 1.2 - v dsqin pin 1&2, sel18v 1&2 input pins (note 11) asserted low --0.8v asserted high 1.7 - - v input current -1- a current sense input bias current i bias - 700 - na over current threshold static current mode, dcl = h 325 400 500 mv error amplifier open loop voltage gain a ol (note 10) 70 88 - db gain bandwidth product gbp (note 10) 10 - - mhz pwm maximum duty cycle 90 93 - % minimum pulse width (note 10) - 20 - ns oscillator oscillator frequency f o fixed at (10)(f tone ) 200 220 240 khz thermal shutdown temperature shutdown threshold (note 10) - 150 - temperature shutdown hysteresis (note 10) - 20 - notes: 8. internal digital soft-start 9. vo1 for lnb1, vo2 for lnb2. voltage programming si gnals vsel1, vsel2, llc1, and llc2 are implemented via the i 2 c bus. io1 = io2 = 350ma/750ma. 10. guaranteed by design. 11. unused dsqin 1&2 pins should be connected to gnd. se l18v1&2 pins have 200k internal pulldown resistors. electrical specifications v cc = 12v, t a = -20c to +85c, unless otherwise noted. typical values are at t a = 25c. en1 = en2 = h, llc1 = llc2 = l, ent1 = ent2 = l, dcl = l, dsqin1 = dsqin2 = l, iout = 12ma, unless otherwise noted. see software description section for i 2 c access to the system. (continued) parameter symbol test conditions min typ max units isl6424
8 fn9175.2 april 13, 2005 functional description the isl6424 dual output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. both supply and control voltage outputs for two low-noise bl ocks (lnbs) are available simultaneously in any output configuration. the device utilizes built-in dc/dc step-conver ters that, from a single supply source ranging from 8v to 14v, generate the voltages that enable the linear post-regulators to work with a minimum of dissipated power. an undervoltage lockout circuit disables the circuit when vcc drops below a fixed threshold (7.5v typ). diseqc encoding the internal oscillator is factor y-trimmed to provide a tone of 22khz in accordance with dise qc (eutelsat) standards. no further adjustment is required. the 22khz oscillator can be controlled either by the i 2 c interface (ent1/2 bit) or by a dedicated pin (dsqin1/2) that allows immediate diseqc data encoding separately for each lnb. (please see note 1 at the end of this section.) all the functions of this ic are controlled via the i 2 c bus by writing to the system registers (sr1, sr2). the same registers can be read back, and two bits will report the diagnostic status. the intern al oscillator operates the converters at ten times the tone frequency. the device offers full i 2 c compatible functionality, 3.3v or 5v, and up to 400khz operation. if the tone enable (ent1/2) bit is set low through i 2 c, then the dsqin1/2 terminal activates the internal tone signal, modulating the dc output with a 0.3v, 22khz, symmetrical waveform. the presence of this signal usually gives the lnb information about the band to be received. burst coding of the 22khz tone can be accomplished due to the fast response of the dsqin1/2 input and rapid tone response. this allows implementation of the diseqc (eutelsat) protocols. typical performance curves figure 1. output current derating (epsoic) figure 2. output current derating (5x5 qfn) note: with both channels in simultaneous operation at rated output 020406080 temperature (c) i out (a) i out _max 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 020406080 temperature (c) i out (a) i out _max 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 functional pin description symbol function sda bidirectional data from/to i 2 c bus. scl clock from i 2 c bus. vsw1, 2 input of the linear post-regulator. pgnd1, 2 dedicated ground for the output gate driver of respective pwm. cs1, 2 current sense input; connect rsc at this pin for desired over current value for respective pwm. sgnd small signal ground for the ic. agnd analog ground for the ic. tcap1, 2 capacitor for setting rise and fall time of the output of lnb a and lnb b respectively. use this capacitor value 1f or higher. bypass bypass capacitor for internal 5v. dsqin1, 2 when high enables internal 22khz modulation for lnb a and lna b respectively, use this pin for tone enable function for lnb a and lnb b. vcc main power supply to the chip. gate1, 2 these are the device outputs of pwm a and pwm b respectively. these high current driver outputs are capable of driving the gate of a power fet. these outputs are actively held low when vcc is below the uvlo threshold. vo1, 2 output voltage of lnb a and lnb b respectively. addr address pin to select two different addresses per voltage level at this pin. comp1, 2 error amp outputs used for compensation. fb1, 2 feedback pins for respective pwms cpvout, cpswin, cpswout charge pump connections. sel18v1, 2 when connected high, th is pin will change the output of the respective pwm to 18v. only available on the qfn package option. isl6424
9 fn9175.2 april 13, 2005 when the ent1/2 bit is set hi gh, a continuous 22khz tone is generated regardless of the ds qin1/2 pin logic status for the corresponding regulator channel (lnb-a or lnb-b). the ent1/2 bit must be set low when the dsqin1 and/or dsqin2 pin is used for diseqc encoding. linear regulator the output linear regulator will si nk and source current. this feature allows full modulation capability into capacitive loads as high as 0.25 f. in order to minimize the power dissipation, the output volt age of the internal step-up converter is adjusted to allow t he linear regulator to work at minimum dropout. when the device is put in the shutdown mode (en1, en2 = low), both pwm power blocks are disabled. (i.e. when en1 = 0, pwm1 is disabled, and when en2 = 0, pwm2 is disabled). when the regulator blocks ar e active (en1 , en2 = high), the output can be logic controlled to be 13v or 18v (typical) by means of the vsel bit (v oltage select) for remote controlling of non-diseqc lnbs. additionally, it is possible to increment by 1v (typical) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (llc1/2 bit high). output timing the programmed output voltage rise and fall times can be set by an external capacitor. the output rise and fall times will be approximately 3400 times the tcap value. for the recommended range of 0.47 f to 2.2 f, the rise and fall time would be 1.6ms to 7.6ms. using a 0.47 f capacitor insures the pwm stays below its overcurrent threshold when charging a 120 f vsw filter cap during the worst case 13v to 19v transition. a typical value of 1.0 f is recommended. this feature only affects the turn-on and programmed voltage rise and fall times. current limiting the current limiting block has two thresholds that can be selected by the isel bit of the sr and can work either statically (simple current clamp) or dynamically. the lower threshold is between 425ma and 550ma (isel = l), while the higher threshold is between 775ma and 950ma (isel = h). when the dcl (dynamic current limiting) bit is set to low, the overcurrent protection circuit works dynamically: as soon as an over load is detected, the output is shutdown for a time t off , typically 900ms. simultaneously the olf bit of the system register is set to high. after this time has elapsed, the output is resumed for a time t on = 20ms. during t on , the device output will be current limited to 425ma min. or 775ma min., dep ending on the isel bits. at the end of t on , if the overload is stil l detected, the protection circuit will cycle again through t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf bit is reset to low. typical t on + t off time is 920ms as determined by an internal timer. this dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions. however, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. this can be solved by initiating any power start-up in static mode (dcl = high) and then switching to the dynamic mode (dcl = low) after a chosen amount of time. when in static mode, the olf1/2 bit goes high when the current limit threshold at the cs pin reaches 0.45v typ and returns low when the overload condition is cleared. the olf1/2 bit will be low at the end of initial power-on soft-start. thermal protection this ic is protected against overheating. when the junction temperature exceeds 150c (typ ical), the step-up converter and the linear regulator are shut off and the otf bit of the sr is set high. normal operation is resumed and the otf bit is reset low when the junction is cooled down to 135c (typical). in over temperature conditions, the otf flag goes high and the i 2 c data will be cleared. the user may need to monitor the i 2 c enable bits and otf flag continuously and enable the chip, if i 2 c data is cleared. otf conditions may also make the olf flags go high, when high capacitive loads are present or self-heati ng conditions occur at higher loads. external output voltage selection the output voltage can be selected by the i 2 c bus. additionally, the qfn package offers two pins (sel18v1, sel18v2) for independent 13v/18v output voltage selection. when using these pins, the i 2 c bits should be initialized to 13v status. i 2 c bus interface for isl6424 (refer to philips i 2 c specification, rev. 2.1) data transmission from main microprocessor to the isl6424 and vice versa takes place through the two wire i 2 c bus interface, consisting of the two lines sda and scl. both sda and scl are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (pull up resistors to positive supply voltage must be externally connected). when the bus is free, both lines are high. the output stages of isl6424 will have an open drain/open collector in order to perform the wired-and function. data on the i 2 c bus can be transferred up to 100kbps table 1. i 2 c bits sel18v (1, 2) o/p voltage 13v low 13v 14v low 14v 13v high 18v 14v high 18v isl6424
10 fn9175.2 april 13, 2005 in the standard-mode or up to 400kbps in the fast-mode. the level of logic ?0? and logic ?1? is dependent of associated value of v dd as per electrical specificat ion table. one clock pulse is generated for each data bit transferred. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. refer to figure 3. start and stop conditions as shown in figure 4, start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition on the sda line while scl is high. a stop condition must be sent before each start condition. byte format every byte put on the sda line must be eight bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transfe rred with the most significant bit first (msb). acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse (figure 5). the peripheral that acknowledges has to pull down (low) the sda line during the acknowled ge clock pulse, so that the sda line is stable low during this clock pulse. (of course, set-up and hold times must also be taken into account.) the peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case , the master transmitter can generate the stop information in order to abort the transfer. the isl6424 will not generate the acknowledge if the power ok signal from the uvlo is low. transmission without acknowledge avoiding detection of the acknowledgement, the microprocessor can use a simple r transmission; it waits one clock without checking the slave acknowledging, and sends the new data. this approach, though, is less protected from error and decreases the noise immunity. isl6424 software description interface protocol the interface protocol is co mprised of the following, as shown below in table 2: ? a start condition (s) ? a chip address byte (msb on left; the lsb bit determines read (1) or write (0) transmission) (the assigned i 2 c slave address for the isl6424 is 0001 00xx) ? a sequence of data (1 byte + acknowledge) ? a stop condition (p) sda scl data line stable data valid change of data allowed figure 3. data validity sda scl start condition figure 4. start and stop waveforms stop condition sp table 2. interface protocol s0001000r/wack data (8 bits) ackp sda scl figure 5. acknowledge on the i 2 c bus 1 2 8 9 acknowledge from slave msb start isl6424
11 fn9175.2 april 13, 2005 system register format ? r, w = read and write bit ? r = read-only bit ? all bits reset to 0 at power-on transmitted data ( i 2 c bus write mode) when the r/w bit in the chip is set to 0, the main microprocessor can write on th e system registers (sr1/sr2) of the isl6424 via i 2 c bus. these will be written by the microprocessor as shown below. the spare bits of sr1/sr2 can be used for other functions. table 3. system register 1 (sr1) r, w r, w r, w r, w r, w r, w r, w r sr1 dcl isel1 ent1 llc1 vsel1 en1 olf1 table 4. system register 2 (sr2) r, w r, w r, w r, w r, w r, w r r sr2 isel2 ent2 llc2 vsel2 en2 otf olf2 table 5. system register (sr1 and sr2) configuration sr dcl isel1 ent1 llc1 vsel1 en1 olf1 function 0 x x x 0 0 x x sr1 is selected 0 x x x 0 0 1 x vout1 = 13v, vboost1 = 13v + vdrop 0 x x x 0 1 1 x vout1 = 18v, vboost1 = 18v + vdrop 0 x x x 1 0 1 x vout1 = 14v, vboost1 = 14v + vdrop 0 x x x 1 1 1 x vout1 = 19v, vboost1 = 19v + vdrop 0 x x 0 x x 1 x 22khz tone is controlled by dsqin1 pin 0 x x 1 x x 1 x 22khz tone is on, dsqin1 is disabled 0 x 0 x x x 1 x iout1 = 425ma max. 0 x 1 x x x 1 x iout1 = 775ma max. 0 1xxxx1xdynamic current limit not selected 0 0xxxx1xdynamic current limit selected 0 x x x x x 0 x pwm and linear for channel 1 disabled sr isel2 ent2 llc2 vsel2 en2 otf olf2 function 1xxxxxxxsr2 is selected 1 x x 0 0 1 x x vout2 = 13v, vboost2 = 13v + vdrop 1 x x 0 1 1 x x vout2 = 18v, vboost2 = 18v + vdrop 1 x x 1 0 1 x x vout2 = 14v, vboost2 = 14v + vdrop 1 x x 1 1 1 x x vout2 = 19v, vboost2 = 19v + vdrop 1 x 0 x x 1 x x 22khz tone is controlled by dsqin2 pin 1 x 1 x x 1 x x 22khz tone is on, dsqin2 is disabled 1 0 x x x 1 x x iout2 = 425ma max. 1 1 x x x 1 x x iout2 = 775ma max. 1 x x x x 0 x x pwm and linear for channel 2 disabled note: otf and olf1&2 are ?read only? bits and x is a ?don?t care? for the function specified. isl6424
12 fn9175.2 april 13, 2005 received data ( i 2 c bus read mode) the isl6424 can provide to the master a copy of the system register information via the i 2 c bus in read mode. the read mode is master activated by sending the chip address with r/w bit set to 1. at the follo wing master generated clock bits, the isl6424 issues a byte on the sda data bus line (msb transmitted first). at the ninth clock bit the mcu master can: ? acknowledge the reception, starting in this way the transmission of another byte from the isl6424. ? not acknowledge, stopping the read mode communication. while the whole register is r ead back by the microprocessor, the read-only bits olf1, olf2, and otf convey diagnostic information about the isl6424. power-on i 2 c interface reset the i 2 c interface built into the is l6424 is automatically reset at power-on. the i 2 c interface block will receive a power ok logic signal from the uvlo circuit. this signal will go high when chip power is ok. as long as this signal is low, the interface will not respond to any i 2 c commands and the system register sr1 and sr2 are in itialized to a ll zeros, thus keeping the power blocks disa bled. once the vcc rises above uvlo, the power ok signal given to the i 2 c interface block will be high, the i 2 c interface becomes operative and the srs can be configured by the main microprocessor. about 400mv of hysteresis is provided in the uvlo threshold to avoid false triggering of the power- on reset circuit. (i 2 c comes up with en = 0; en goes high at the same time as (o r later than) all other i 2 c data for that pwm becomes valid). address pin connecting this pin to gnd the chip i 2 c interface address is 0001000, but, it is possible to choose between two different addresses simply by setting this pin at one of the two fixed voltage levels as shown in table 8. i 2 c electrical characteristics table 6. address pin characteristics v addr minimum typical maximum v addr -1 ?0001000? 0v - 2v v addr -2 ?0001001? 2.7v - 5v table 7. reading system registers dcl isel1/2 ent1/2 llc1/2 vsel1/ 1 en1/2 otf2 olf1/2 function these bits are read as they were after the last write operation. 0 t j 130c, normal operation 1t j > 150c, power blocks disabled 0i out < i max , normal operation 1i out > i max , overload protection triggered table 8. i 2 c specifications parameter test condition minimum typical maximum input logic high, vih sda, scl 0.7 x v dd input logic low, vil sda, scl 0.3 x v dd input logic current, iil sda, scl; 0.4v < v in < 4.5v 10 a scl clock frequency 0 100khz 400khz isl6424
13 fn9175.2 april 13, 2005 isl6424 small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m p1 n 123 top view side view bottom view p m28.3b 28 lead wide body smal l outline exposed pad plastic package symbol inches notes min nominal max a 0.091 - 0.099 - a1 0.001 - 0.005 - b 0.014 - 0.019 9 c 0.0091 - 0.0125 - d 0.701 - 0.711 3 e 0.292 - 0.299 4 e 0.050 bsc - h 0.400 - 0.410 - h 0.010 - 0.016 5 l 0.024 - 0.040 6 n287 0 5 8 - p 0.180 0.214 0.218 11 p1 0.156 0.190 0.194 11 rev. 0 5/02 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optiona l. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: inch. 11. dimensions ?p? and ?p1? are thermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count body size.
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9175.2 april 13, 2005 isl6424 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l32.5x5 32 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-2 issue c symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n322 nd 8 3 ne 8 8 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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